The present invention relates to a matrix-type display device, and more particularly, to a matrix-type display which can be repaired in a pixel unit.
As an interface between a person and a computer, there are provided various flat panel display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminesence (EL) and field emission display (FPD), instead of a conventional cathode ray tube (CRT). These flat panel display devices adopt a matrix-type wiring layout in which horizontal and vertical signal lines cross at right angles. This matrix-type wiring layout will be described with reference to the appended drawings.
FIG. 1 is a plan view showing the layout of a matrix-type display device.
As shown in FIG. 1, in the conventional matrix-type display device, a plurality of scanning signal lines G1, G2,  . . . , Gm are parallel formed in the horizontal direction and a plurality of displaying signal lines D1, D2, D3, D4, . . . , D2nπ1 and D2n are formed in the vertical direction, which crosses with the scanning signal lines while an insulating layer is interposed therebetween.
Each one end of the scanning signal lines G1, G2, . . . , Gm has input pads GP1, GP2, . . . , GPm to which signals are input, and each one end of the displaying signal lines D1, D2, D3, D4, . . . , D2nπ1 and D2n also has input pads DP1, DP2, DP3, DP4, . . . , DP2nπ1 and DP2. Here, the input pads of the displaying signal lines D1, D3, . . . and D2nπ1 are formed at upper part of the matrix wiring layout, and the displaying signal lines D2, D4,  . . . and D2n have the input pads which are formed at bottom part of the wiring layout.
On the other hand, a pixel (PX) is formed in each space formed by the cross of the scanning signal lines G1, G2, . . . , Gm and the displaying signal lines D1, D2, D3, D4, . . . , D2nπ1 and D2n, with a matrix arrangement. Here, the layout of the pixel may be various according to the type of the display device.
The LCD as one of the flat panel display devices which have been highlighted recently adopts an electro-optical effect of a liquid crystal material. The driving mode of the LCD is roughly classified into a simple matrix type and an active matrix type.
According to the active matrix type LCD, a switching element having a non-linear characteristic is appended to each pixel with the matrix arrangement to control the operation of each pixel. Here, a thin film transistor (TFT) of three-terminals type is generally used as the switching element and a thin film diode (TFD) such as a metal insulator metal (MIM) of two-terminals type may be used for the switching element.
Especially, the LCD adopting a TFT as the switching element is comprised of a TFT, a pixel electrode, a TFT substrate on which scanning signal lines or gate lines for supplying a scanning signal or a switching signal and displaying signal lines or data lines for supplying a displaying signal or an image signal are formed, an opposing substrate on which a common electrode is formed, and a liquid crystal material which is injected between the TFT substrate and the opposing substrate.
Hereinafter, the pixel layout of the TFT-LCD will be described with reference to FIG. 2.
FIG. 2 is a diagram showing a conventional TFT-LCD. Each pixel (PX) includes a TFT formed on a lower substrate (TFT substrate), a liquid crystal capacitor (Clc) comprised of a pixel electrode 10 as a lower substrate, a common electrode (CE) as an opposing upper substrate and a liquid crystal material filled between two electrodes, and a storage capacitor (Cst) formed on the lower substrate Here, the storage capacitor (Cst) stores a signal applied to the pixel PX for a predetermined time lapse. On the other hand, the pixel PX is connected to a data line and a gate line via the TFT. For example, three terminals of the TFT are connected to the data line, the gate line and the pixel electrode 10, respectively. However, in FIG. 2, the TFT for switching a corresponding pixel (PX) exists outside the pixel, that is, a terminal of the TFT is connected to a pixel electrode of the adjacent pixel to drive the adjacent pixel. On the contrary, a TFT for driving a pixel may be formed in the corresponding pixel.
The display operation of the LCD is as follows. A predetermined voltage or a periodic voltage is applied to the common electrode CE, and a voltage is applied to the pixel electrode 10 via the TFT. Consequently, the display operation is performed by the electro-optical effect of the liquid crystal material composing the liquid crystal capacitor Clc.
Referring to FIGS. 3 and 4, the plan layout and the vertical layout of the TFT substrate corresponding to the lower substrate of the LCD having the layout as shown in FIGS. 1 and 2 will be described.
FIG. 3 is a plan view of showing the layout of the TFT substrate corresponding to the lower substrate of the LCD shown in FIG. 2. Here, the gate line has an layout of a closed carve enclosing the pixel electrode. FIG. 4 is a sectional view of a portion cut along a line A—A shown in FIG. 3. Here, the regions represented by PXi (i=1, 2, 3, 4), having a rectangular-like form, correspond to the lower portion of a pixel. For convenience' sake, let's call the rectangular-like regions including the gate line and the data line as “pixel” or “pixel region.” Also, let's call a set of pixels formed in the horizontal direction and a set of pixels formed in the vertical direction as “pixel row” and “pixel column”, respectively.
As shown in FIGS. 3 and 4, the up and down gate lines Gup and Gdown are formed on a transparent insulating substrate in the above and below of a pixel row. The down gate line Gdowm extends straight in the horizontal direction. The up gate line Gup is comprised of a first horizontal portion Gh1 which is the longest portion thereof, a first vertical portion Gv1 extending downward from the end of the first horizontal portion Gh1, a second horizontal portion Gh2 extending in the horizontal direction from the end of the first vertical portion Gv1, and a second vertical portion Gv2 extending upward from the end of the second horizontal portion G2. This layout of the up gate line Gup is duplicated with respect to each pixel. Generally, the above dual layout of the gate line called a dual gate line layout.
The first horizontal portion Gh1 of the up gate line Gup and the down gate line Gdown are connected by a left auxiliary gate line 1a, and the second vertical portion Gv2 of the up gate line Gup is lengthened downward to form a right auxiliary gate line 1b reaching the down gate line Gdown.
A data line D is vertically formed between each pixel column and crosses with the first horizontal portion Gh1 of the up gate line line Gup and the down gate line Gdown via an gate insulating layer 4 (see FIG. 4).
The up and down gate lines Gup and Gdown and a pair of left and right auxiliary gate lines 1a and 1b are formed a closed curve as a black matrix. In the region defined by the closed curve, there is formed the pixel electrode 10 with which the gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b are overlapped while the gate insulating layer 4 (see FIG. 4) and a protection layer 9 (see FIG. 4) which will be described later are interposed between the pixel electrode 10 and gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b. Here, the overlapped portion plays as the storage capacitor Cst (see FIG. 2). This storage capacitor formed in a closed curve is called “ring capacitor.” Also, only the up and down gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b forming the ring capacitor may call a ring capacitor for short. Here, a ring capacitor means the latter.
It is preferable that the gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b have the above layout of a closed curve to surround the pixel electrode since a signal can be transferred even if the part of the gate lines Gup and Gdown and the auxiliary gate lines 1a and 1b are disconnected.
On the other hand, a TFT is formed on the second vertical portion Gv2 of the up gate line Gup, which will be described in detail with reference to FIGS. 3 and 4.
First, a part of the second vertical portion Gv2 becomes a gate electrode 2 of the TFT. When the gate lines Gup and Gdown are made of material which enable to be anode oxidation, such as aluminum, the remaining portion other than a gate pad (not shown) electrically connecting the gate lines Gup and Gdown with the outside is anode-oxidized in general. Thus, a gate oxide layer 3 which is anode-oxidized exists on the gate electrode 2. The gate insulating layer 4 is formed on the whole surface of the gate oxide layer 3 excluding the gate pad.
A semiconductor layer 5 is formed covering the gate electrode 2 while the gate insulating layer 4 is interposed therebetween. The semiconductor layer 5 is also formed on the gate lines Gup and Gdown to prevent a short between the gate lines Gup and Gdown and the data line D. Generally, the semiconductor layer 5 is made of amorphous silicon or polysilicon.
A contact layer 6 for improving an ohmic contact between the semiconductor layer 5 and a metal is formed on the semiconductor layer 5, which is generally made of n+ amorphous silicon doped with n+ impurities of a high concentration. In FIG. 3, the pattern of the contact layer 6 is formed on a portion in which the semiconductor layer 5 is overlapped with a source electrode 7 and a drain electrode.
The source electrode 7 as a branch of the data line D and the drain electrode 8 being separated from the source electrode 7 are formed on the contact layer 6. Since the source electrode 7 locates near a cross point between the up gate line Gup and the data line D, the source electrode 7 may be overlapped with the second vertical portion Gv2 of the up gate line Gup as shown in FIG. 3. One end of the drain electrode 8 opposites to the source electrode 7 while the gate electrode 2 is interposed therebetween, and the other end of the drain electrode 8 is connected to the pixel electrode 10 of the upper pixel in the same pixel column while being overlapped with the down gate line Gdown of the upper pixel. For example, as shown in FIG. 3, the drain electrode 8 of the pixel PX2 is connected to the pixel electrode 10 of the pixel PX1 which is the upper pixel of the same pixel column, while being overlapped with the down gate line Gdown located beneath the pixel electrode 10 of the pixel PX1.
A protection layer 10 is covered on the resultant surface in which the source electrode 7 and the drain electrode 8 are formed, excluding on the contact portion between the drain electrode 8 and the pixel electrode 10 and a pad (not shown), and the pixel electrode 10 made of a transparent conductive material is formed on the protection layer 9.
In the pixel layout shown in FIG. 3, a TFT (including a gate electrode, a source electrode and a drain electrode) formed in a pixel region does not drive the pixel of the pixel region. However, for the convenience' sake, the TFT will be called “the TFT of the pixel” through the whole specification.
In this flat panel display device, particularly, in the TFT substrate for the LCD, there are wirings such as gate and data lines for supplying a signal to the pixel as described above. These wirings may be easily disconnected or shortened by a topographical characteristic of the region through which the wiring passes or by the subsequent heating and etching processes. If the wiring is disconnected or shortened, a signal required for the pixel cannot be properly applied. As a result, the displaying function cannot be performed smoothly.
On the other hand, in the case of the LCD having the gate lines' layout including the up, down gate lines Gup, Gdown and auxiliary gate lines 1a and 1b, the disconnection of the gate lines Gup, Gdown, 1a and 1b can be easily repaired. If the data line D is disconnected, an image signal cannot be transferred to a portion following the shortened point. Also, if the pixel electrode 10 and the gate lines Gup, Gdown, 1a and 1b are shortened, and the gate electrode 2 is lost or damaged, it is impossible to repair the drawback.
To solve the above problem, many trials have been performed. According to a solution from many trials, a repair line is formed in a closed curve around a screen having the pixels to cross the gate line and the data line while a gate insulating layer is interposed between the gate and data lines and the repair line, so that the repair line can replace the disconnected wiring if a specific wiring is disconnected.
Then, the conventional matrix-type display device in which a repair line is formed in a closed curve around a screen will be described in detail with reference to FIG. 5.
As shown in FIG. 5, a repair line RL made of a conductive material is formed in a closed curve around a region in which a plurality of pixels formed by crossing a plurality of linear scanning signal lines G1, G2, . . . , Gm which are parallel each other in the horizontal direction and a plurality of linear displaying signal lines D1, D2, D3, D4, . . . , D2nπ1 and D2n which crosses the linear scanning signal lines at a right angle are formed. The repair line RL crosses each or scanning signal lines G1, G2, . . . , Gm once at the one side of the scanning signal lines and each of displaying signal lines D1, D2, D3, D4,  . . . , D2nπ1 and D2n twice at the upper and lower sides. Here, the repair line RL, the scanning signal lines G1, G2, . . . , Gm and the displaying signal lines D1, D2, D3, D4, . . . , D2nπ1 and D2n are formed while an insulating layer is interposed therebetween, so that each cross portion formed therebetween is used as a capacitor.
Hereinafter, the operation of the matrix-type display device will be described in detail.
A switching signal is applied to the pixel electrode 10 in sequence via the plural scanning signal lines G1, G2, . . . , Gm formed in the horizontal direction. Then, according to the above appliance, an image signal is applied to the corresponding pixel electrode 10 via the displaying signal lines D1, D2, D3, D4, . . . , D2nπ1 and D2n.
On the other hand, as shown in FIG. 5, supposing that a displaying signal line D3 is disconnected. Here, the disconnection occurs at a point represented by a mark “≈.” In this case, an image signal applied via the displaying signal line D3 reaches to just the disconnect point. That is, the image signal does not reach to a displaying signal line portion following the disconnect point.
Hereinafter, let's consider a method for making a signal to reach the displaying signal line portion following the disconnect point using the repair line RL. For the purpose, the upper and lower cross points between the displaying signal line D3 and the repair line RL, represented by a rectangle, are shortened using a laser. When the pixel connected to the displaying signal line D3 following the disconnect point is opened, a signal from the input pad DP3 passes the shortened upper cross point and then moves from the cross portions to a left path P1 or a right path P2 of the displaying signal line D3 along the repair line RL connected to the displaying signal line D3. However, since the path P2 is longer than the path P1 and crosses with more displaying signal lines compared with the path P1, the signal movement along the path P2 is inefficient. Thus, it is required to move the signal along only the path P1 while blocking the signal movement along the path P2. For blocking the signal movement along the path P2, two points on the path P2, which are near the short points represented by the rectangles and represented by a mark “x”, are cut. As a result, the signal can be applied to the displaying signal line D3 following the disconnect point via the path P1 of the repair line RL.
On the other hand, the signal applied via the path P1 should pass cross points a and a′ each formed between the displaying signal lines D1 and D2 and the repair line RL. However, as described above, the cross points a and a′ function as a capacitor which distorts the image signal moving along the repair line RL. Particularly, the number of the displaying and scanning signal lines increases as the size of the screen increase. Consequently, the number of the cross points existing on the path along which the signal moves also increases. That is, the number of the capacitors increases and the overall static capacitance also increases. Also, since the length of the repair line RL increases, resistance increases. Due to the above reasons, the signal moving along the repair line RL may be further distorted by a RC time delay.
Also, the number of the displaying signal lines D1, D2, D3, D4, . . . , D2nπ1 and D2n which can be repaired using the repair line RL is limited due to the limitation of a space.